1. Field of the Invention
The present invention relates to a dynamic type semiconductor memory device having a sense amplifier for amplifying and outputting a micro signal on a bit line.
2. Description of the Related Art
The arrangement of a sense amplifier section in a conventional dynamic type semiconductor memory device (to be referred to as a DRAM hereinafter) is shown in FIG. 1, and operational waveforms thereof are illustrated in a timing chart in FIG. 2.
That is, when a signal from a word line WL rises, a MOS transistor 1 in a memory cell MC is turned on, and a signal corresponding to data stored in a capacitor 2 is read to a bit line BL, thereby generating a micro potential difference between a pair of bit lines BL and BL. Thereafter, when a signal from a sense amplifier control line SAN for activating an n-channel side sense amplifier consisting of two n-channel MOS transistors 3 and 4 is dropped from 0.5.multidot.V.sub.CC to V.sub.SS, a potential of the low-potential side bit line (BL in FIG. 2) is decreased sequentially from 0.5.multidot.V.sub.CC to V.sub.SS. Thereafter, when a signal from a sense amplifier line SAP for activating a p-channel side sense amplifier consisting of two p-channel MOS transistors 5 and 6 is raised from 0.5.multidot.V.sub.CC to V.sub.CC' a potential of the high-potential side bit line (BL in FIG. 2) is increased sequentially from 0.5.multidot.V.sub.CC to V.sub.CC. When the potential difference between the bit lines BL and BL is sufficiently large, a signal from a column selecting line CSL is raised, and a pair of column selecting n-channel MOS transistors 7 and 8 are turned on, thereby causing a signal to appear from a pair of input/output lines DQ and DQ precharged to be V.sub.CC in advance.
In a conventional DRAM, a signal from a pair of bit lines cannot be disadvantageously transmitted to a pair of data input/output lines at a high speed, because a potential of the column selecting line CSL cannot be raised unless the potential difference between a pair of bit lines is sufficiently amplified. If the potential of the column selecting line CSL is raised when the potential difference between the pair of bit lines is small, the potentials of the pair of bit lines come to a floating state due to an entrance of charges from the precharged to the pair of data input/output lines, and data may be erroneous due to unbalance of the potentials of the pair of bit lines. In addition, when an integration density of memory cells in a DRAM is increased, a time required for amplifying the potential difference between the pair of bit lines is further prolonged. Therefore, since a delay time of the sense amplifier section occupies a very large part in an access time, the delay time will be further increased in the future.